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Company
Intel Technology India Pvt. Ltd
Website
www.intel.in
Eligibility
B.E./B.Tech
Experience
2 - 3 yrs
Location Bengaluru/Bangalore
Job Role
Senior Logic Design
Engineer
JOB SUMMARY:
Comapny profile :
IBM is a global technology and innovation
company headquartered in Armonk, NY. It is the largest technology
and consulting employer in the world, with more than 400,000 employees
serving clients in 170 countries. IBM offers a wide range of technology
and consulting services; a broad portfolio of software development
and systems management; and the world's most advanced servers and
supercomputers. Utilizing its business consulting, technology and
R&D expertise, IBM helps clients become "smarter" as
the planet becomes more digitally interconnected. IBM invests more
than $6 billion a year in R&D, just completing its 18th year of
patent leadership.
Job Description:
Component Design Engineers are responsible
for the design and development of electronic components. Responsibilities
may include: the design of chip layout circuit design, circuit checking,
device evaluation and characterization, documentation of specifications,
prototype construction and checkout, modification and evaluation of
semiconductor devices and components, performing developmental and/or
test work, reviewing product requirements and logic diagrams, planning
and organizing design projects or phases of design projects. Responds
to customer/client requests or events as they occur. Develops solutions
to problems utilizing formal education and judgement.
CandidatePrfile:
Master of Science (or a Master of Technology)
degree in Electronics and or Electrical Engineering or a Bachelor
of Science (Bachelor of Technology) degree in electronics and or Electrical
Engineering.
Familiar with connectivity fabrics such as OCP, APB and I/O buses
such as PCIE, I2C, SPI, UART etc. highly desired
Person should be a team player and should be able to work with other
teams effectively so as to reuse IP and rapidly develop designs.
7+ years experience as a unit RTL design owner for complex IPs on
large ICs/SoCs, required.
At least 5 years in SystemVerilog or Verilog coding, required, knowledge
of OVL/SVA assertions and Static timing analysis highly desired
2 years experience in coverage-driven functional verification, test
plan development and test plan execution desirable.
Expertise in one scripting language like to perl/tcl, shell etc is
a must.
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